In datasheet on some ICs (e.g. DM74LS374), I noticed the features that "P-N-P inputs reduce D-C loading on the data lines". What is that meant for? Can anyone please help me on this?
In standard TTL ICs, there are NPN Transistors with multiple emitters, which serve as input lines. To tie such an input to low state, a considerable current is drawn from the input. I can't remember the values now, but the current for low input is some ten times greater than the current for high state. An additional PNP transistor can open with the 0 voltage applied
to his base and thus provide the emmiter current
to the mentioned mutiemitter transistor or
to whatever they designed as the nextstage.
This will allow you to connect more such IC input pins to an output pin.
