how to mask 1 bit in a register in Cimplicity HMI?


Thread Starter

Frank Deprest

In Cimplicity HMI version 6 I want to do the following:

To limit the amount of I/O's between the PLC and Cimplicity, we put 31 successive flags (virtual Cimplicity points) in 1 register. The PLC then 'disassembles' this register into real PLC-flags. The problem is when we want to reset such a flag (for set we use a or-function in the script: pointset reg,(2^offset or valreg) where valreg is the value of the register before we do the pset and offset the bitposition in the register;x^y=x to the power y )

We can't reset the whole register because other flags have to be still in a high-state.

Short example (4 bits):
in the sequence: 1001 I want to reset the first bit on the left. I tried with a xor:
1001 xor 1000=0001 (pset reg,(valreg xor 2^offset)) that's ok, but
0001 xor 1000=1001: not what I want, a state low changes in high (0001 xor 0=0001 is good for me, but when to know if you have to xor with zero or 2^offset?)!

Please help me (the available logic functions in Cimplicity: and, or, not, xor and shr,shl).
Can the software do a subtract of 2^bit# ? I.e. 1001-1000=0001

What if you do an AND with NOT of 2^bit# ? I.e. [ 1001 AND NOT(1000) ] = 1001 AND 0111 = 0001


Walters Curt L Contr AEDC/SVT


Try this:
1. Take the complement of your register
2. Or it with the 2^offset which indicates the desired bit position to reset
3. Take the complement of the result.

You can complement by XOR with all ones.

I tried it with the two cases you mentioned and it seems to work.
1. 1001 XOR 1111 = 0110
2. 0110 OR 1000 = 1110
3. 1110 XOR 1111 = 0001

1. Change 0001 to 1110
2. 1110 OR 1000 = 1110
3. Change 1110 to 0001

Hope this Helps.

Frank Deprest

The problem has been solved with the solution which first inverted the mask (2^offset) and then AND-ed with the contents of the PLC-register.

The solution with a xor is false, it replaces 0's with 1's! (0 (PLC-register content) xor 1 (content mask register)=1 if you invert first the mask register)