IEC 870 5 101 protocol - what is it?

L

Thread Starter

Laurent

Hi !

My customer have a scada system using the ICE870-5-101 protocol. I need to install several S7-300 and they need to dial with the scada.
It's fist time I see this protocol, usually I use Modbus.
Anybody know this protocol ?


 
M

Moises Ali Cure

File: PP870TS.USA Release: April 1997

Normative references

IEC 870-5-1 Transmission frame formats
IEC 870-5-2 Link transmission procedures
IEC 870-5-3 General structure of application data
IEC 870-5-4 Definition and coding of application informations
elements
IEC 870-5-5 Basic application functions
IEC 870-5-101 Companion standard for basic telecontrol tasks

The companion standard ..-101 admits exclusively frame formats FT1.2 that is defined in IEC 870-5-1. Formats with fixed and with variable block length ara admitted. Also the single control character I (E5) transmission is admitted.


Transmission rules

R1 Line idle is binary 1.

R2 Each character has one start bit (binary 0), 8 information bits,
one even parity bit and one stop bit (binary 1).

R3 No line idle intervals ara admitted between characters of a frame.

R4 Upon detecting an error according to rule R6, a mimimum interval
of 33 line idle bits is required between frames.

R5 The sequence of user data characters is terminated bay a 8 bits
check sum (CS). The check sum is the arithmetic sum disregarding
overflows (sum modulo 256) over all user data octets.

R6 The receiver checks:

per character:
the start bit, the stop bit and the even parity bit;

per frame:
the specified start character at the beginning and at the end of the frame header, the identity of the two length specifications L, that the number of received characters is equal to L + 6, the frame check sum, the end character, upon detecting an error, the line idle interval specified by R4.

The frame is rejected if one of these checks fails, otherwise it is released to the user.
 
M

Moises Ali Cure

Type of messages

M_SP_NA_1 1 Single-point information
M_SP_TA_1 2 Single-point information with time tag
M_DP_NA_1 3 Double-point information
M_DP_TA_1 4 Double-point information with time tag
M_ST_NA_1 5 Step position information
M_ST_TA_1 6 Step position information with time tag
M_BO_NA_1 7 Bitstring 32 bit;
M_BO_TA_1 8 Bitstring 32 bit with time tag
M_ME_NA_1 9 Measured value, normalized value
M_ME_TA_1 10 Measured value, normalized value with time tag
M_ME_NB_1 11 Measured value, scaled value
M_ME_TB_1 12 Measured value, scaled value with time tag
M_ME_NC_1 13 Measured value, short floating point number
M_ME_TC_1 14 Measured value, short floating point number with time tag
M_IT_NA_1 15 Integrated totals;
M_IT_TA_1 16 Integrated totals with time tag
M_EP_TA_1 17 Event of protection equipment with time tag
M_EP_TB_1 18 Packed start events of protection equipment with time tag
M_EP_TC_1 19 Packed ouput circuit information of protection equipment
with time tag
M_PS_NA_1 20 Packed single-point information with status change detection
M_ME_ND_1 21 Measured value, normalized value without quality descriptor

C_SC_NA_1 45 Single command
C_DC_NA_1 46 Double command
C_RC_NA_1 47 Regulating step command
C_SE_NA_1 48 Set point command, normalized value
C_SE_NB_1 49 Set-point command, scaled value
C_SE_NC_1 50 Set-point command, short floating point number
C_BO_NA_1 51 Bitstring of 32 bits

M_EI_NA_1 70 End of initialization

C_IC_NA_1 100 Interrogation command
C_CI_NA_1 101 Counter interrogation command
C_RD_NA_1 102 Read command
C_CS_NA_1 103 Clock synchronization command
C_TS_NA_1 104 Test command
C_RP_NA_1 105 Reset process command
C_CD_NA_1 106 Delay acquisition command

P_ME_NA_1 110 Parameter of measured value, normalized value
P_ME_NB_1 111 Parameter of measured value, scaled value
P_ME_NC_1 112 Parameter of measured value, short floating point number
P_AC_NA_1 113 Parameter activation

F_FR_NA_1 120 File ready
F_SR_NA_1 121 Section ready
F_SC_NA_1 122 Call directory, select file, call file, call section
F_LS_NA_1 123 Last section, last segment
F_AF_NA_1 124 Ack file, ack section
F_SG_NA_1 125 Segment
F_DR_TA_1 126 Directory


Cause of transmission

ori Originator address
per/cyc 1 periodic, cyclic
back 2 background scan
spont 3 spontaneous
init 4 initialized
req 5 request or requested
act 6 activation
actcon 7 activation confirmation
deact 8 deactivation
deactcon 9 deactivation confirmation
actterm 10 activation termination
retrem 11 return information caused by a remote command
retloc 12 return information caused by a local command
file 13 file transfer

inrogen 20 interrogated by general interrogation
inro1 21 interrogated by group 1 interrogation
inro2 22 interrogated by group 2 interrogation
inro3 23 interrogated by group 3 interrogation
inro4 24 interrogated by group 4 interrogation
inro5 25 interrogated by group 5 interrogation
inro6 26 interrogated by group 6 interrogation
inro7 27 interrogated by group 7 interrogation
inro8 28 interrogated by group 8 interrogation
inro9 29 interrogated by group 9 interrogation
inro10 30 interrogated by group 10 interrogation
inro11 31 interrogated by group 11 interrogation
inro12 32 interrogated by group 12 interrogation
inro13 33 interrogated by group 13 interrogation
inro14 34 interrogated by group 14 interrogation
inro15 35 interrogated by group 15 interrogation
inro16 36 interrogated by group 16 interrogation
reqcogen 37 requested by general counter request
reqco1 38 requested by group 1 counter request
reqco2 39 requested by group 2 counter request
reqco3 40 requested by group 3 counter request
reqco4 41 requested by group 4 counter request


Qualifier

BL blocked
NT not topical
IV invalid
SB substituted
OV overflow
indet indeterminate state
res reserve
SU summertime
T test
TR transient state
SQ sequence number
CA counter was adjusted
CY counter overflow
EI elapsed time invalid
GS general start of operation
SL1 start of operation phase L1
SL2 start of operation phase L2
SL3 start of operation phase L3
SIE start of operation IE (earth current)
SRD start of operation in reverse direction
GC general command to output circuit
CL1 command output circuit phase L1
CL2 command output circuit phase L2
CL3 command output circuit phase L3
 
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