LLAG function (PCFL Modicon LL, Concept 2.6)


Thread Starter

Tim Schleining


I'm fairly new to programming in Concept ladder logic, and am not clear on how I would set up a PCFL block for lead/lag. I do have the "Modicon Ladder Logic Block Library User Guide", but the entire section on PCFL remains partly cloudy for me.

I guess my confusion is with all of the registers. The user guide has a table with parameter block assignments for all 20 registers, and I'm STILL confused.

Assuming that I were to use MOVE blocks to fill the registers,

which register do I move the current PV to? 1st, 10th, or 11th?

Which register would I put the solution interval in? I see that the fourth implied register is the "Time register"... would that be it, or is it the 8th or 9th implied registers? (They say solution interval, in ms).

Why do the lead, lag, and filter gain terms have two registers each? Same with the result?

Very confused and looking for an example. My documentation only provides the table, no examples.

Thanks in advance.