Phase Detector (Phase lock loop)


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I have a linear model of a phase detector (phase lock loop), presented by a block diagram, which i have tried to create below. Which is required to maintain zero phase difference between the input carrier signal and a local voltage controlled oscillator.<pre>
Phase Demand - Ka - F(s) - K/s - Phase Output

F(s) = 10(s+10)/(s+1)(s+100)</pre>
We want to minimise the steady state error for a ramp change in the phase information signal.

Please help me to determine the limiting value of the gain KaK=Kv in order to maintain a stable system.