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Hi,
I am having a problem developing a PID controller with input as a signal with units (time/revolution). This signal is inversely proportional to the normal velocity signal. The point is, we are trying at all cost to avoid signal invertion in the FPGA implementation.
The system consists of two loops, an outer PID rate (time/rev) control loop which should output a current. This current is then fed into an inner loop current controller (PID also) which then outputs a voltage, which is fed into the motor.
So far, I have negated the output of the current controller on the basis that if a > b then 1/a < 1/b. Performance at start-up seemed ok, but after a while the output velocity suddenly derails from its set point value. Also to be noted, the current is limited to +/-1A and the voltage to +/-10V. If anyone could give me some ideas I could further implement to arrive at succesful results, I would be very grateful.
Thanks in advance...
I am having a problem developing a PID controller with input as a signal with units (time/revolution). This signal is inversely proportional to the normal velocity signal. The point is, we are trying at all cost to avoid signal invertion in the FPGA implementation.
The system consists of two loops, an outer PID rate (time/rev) control loop which should output a current. This current is then fed into an inner loop current controller (PID also) which then outputs a voltage, which is fed into the motor.
So far, I have negated the output of the current controller on the basis that if a > b then 1/a < 1/b. Performance at start-up seemed ok, but after a while the output velocity suddenly derails from its set point value. Also to be noted, the current is limited to +/-1A and the voltage to +/-10V. If anyone could give me some ideas I could further implement to arrive at succesful results, I would be very grateful.
Thanks in advance...
