B
<P>Good day, Siemens experts.</P>
<P>I am supplying a retrofit; replacing Siemens Step 5 PLC with ControlLogix. Generally, the machinery is not difficult to understand with the
exception of a few details I am reverse engineering from the Step 5 PLC program.
I do not have experience with the Step 5, but I thought I was generally able to read and understand the code. Except for the following logic:</P>
<PRE>
Segment 66
-I34.1 -I34.2 -F128.4 -I34.3 -F128.0
+---] [---+---] [---+---(#)---+---]/[---+---------+--( )-+
! !
!-T86 !
+---]/[---+
Segment 67
-T86
-F128.4 +-----+
+---] [---+-!T!-!0!
!KT 050.0 --!TV BI!
! ! DE!
! ! !
! ! !
! +-!R Q!-
! +-----+
</PRE>
<P>My pea brain thinks that F128.4 is an edge trigger that passes power while devices on I34.1 and I34.2 are closed. So, continuing along, F128.0 is true while device I34.3 is open or T86 is not timed out. Seems simple.</P>
<P>But in 67, if I understand the Step 5 manual, I see the timer never timing out. I think that T!-!0 describes an on-delay timer that times for 50 * 0.01 = 0.5 seconds while T!-!0 is true. But it will never see the edge trigger F128.4 long enough
to allow that to happen. If the -] [- instruction in 67 was -]/[- it would make sense to me.</P>
<P>It looks to be a minimum time limit on the period that output F128.0 is true, but I can't see it.</P>
<P>What am I missing here?</P>
<P>Bill Code<BR>
604-513-8049<BR>
KR Consulting Ltd.<BR>
Surrey, B.C., Canada<BR>
<P>I am supplying a retrofit; replacing Siemens Step 5 PLC with ControlLogix. Generally, the machinery is not difficult to understand with the
exception of a few details I am reverse engineering from the Step 5 PLC program.
I do not have experience with the Step 5, but I thought I was generally able to read and understand the code. Except for the following logic:</P>
<PRE>
Segment 66
-I34.1 -I34.2 -F128.4 -I34.3 -F128.0
+---] [---+---] [---+---(#)---+---]/[---+---------+--( )-+
! !
!-T86 !
+---]/[---+
Segment 67
-T86
-F128.4 +-----+
+---] [---+-!T!-!0!
!KT 050.0 --!TV BI!
! ! DE!
! ! !
! ! !
! +-!R Q!-
! +-----+
</PRE>
<P>My pea brain thinks that F128.4 is an edge trigger that passes power while devices on I34.1 and I34.2 are closed. So, continuing along, F128.0 is true while device I34.3 is open or T86 is not timed out. Seems simple.</P>
<P>But in 67, if I understand the Step 5 manual, I see the timer never timing out. I think that T!-!0 describes an on-delay timer that times for 50 * 0.01 = 0.5 seconds while T!-!0 is true. But it will never see the edge trigger F128.4 long enough
to allow that to happen. If the -] [- instruction in 67 was -]/[- it would make sense to me.</P>
<P>It looks to be a minimum time limit on the period that output F128.0 is true, but I can't see it.</P>
<P>What am I missing here?</P>
<P>Bill Code<BR>
604-513-8049<BR>
KR Consulting Ltd.<BR>
Surrey, B.C., Canada<BR>