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Hello
I am trying to understand how Px class CTs work. We have been asked to implement two differential protection schemes, one line differential and the other transformer differential.
For line differential protection, the CT's are being fed into two individual electronic differential protection relays which communicate via fiber link (i.e. by Schneider). One CT is existing and ~20 years of age the other is new. Existing CT is 1250/1A 10P20 and new one is specified as 10P20 1250/1A. Maximum fault level at the end of the line (i.e. outside the differential zone) is 40kA (RMS symmetrical) and 70kA (RMS asymmetrical).
It is assumed that the knee point (i.e. saturation limit) for both CT's is similar. My understanding is, for a through fault (assume 70kA asymmetrical), both sets of CTs will hit their saturation limit and provide a similar level of saturated current to the relays. For a fault level below the saturation limit (i.e. high impedance earth fault), the CT's will not saturate and provide some level of secondary current to the relays with a guaranteed error of 10%. How do we ensure the differential relays do not trip with this level of error? Is it just a matter of decreasing the sensitivity such that they only trip for currents >10% of 20x In? For example, 10% of 20 x 1250 = 2500A?
For transformer differential, the CT's are new and are both feeding into one electronic differential protection relay (ie. by Schneider). Supplier of the switchboard feeding the transformer has nominated class Px CT's (i.e. 1250/1A .025PX100R1.5). My understanding of this notation is that, 100 is the knee point voltage (i.e. where CT saturates), R1.5 is the CT winding resistance, however what does the 0.025 mean? Also, as the knee point is given in terms of voltage and not a multiple of ratio, how do you know what level of primary current will force the CT into saturation? If you don't know this level of current, how do you ensure both sets of CT's (i.e. upstream/downstream of the transformer) will be sized such that they do not trip on through faults?
Thanks
I am trying to understand how Px class CTs work. We have been asked to implement two differential protection schemes, one line differential and the other transformer differential.
For line differential protection, the CT's are being fed into two individual electronic differential protection relays which communicate via fiber link (i.e. by Schneider). One CT is existing and ~20 years of age the other is new. Existing CT is 1250/1A 10P20 and new one is specified as 10P20 1250/1A. Maximum fault level at the end of the line (i.e. outside the differential zone) is 40kA (RMS symmetrical) and 70kA (RMS asymmetrical).
It is assumed that the knee point (i.e. saturation limit) for both CT's is similar. My understanding is, for a through fault (assume 70kA asymmetrical), both sets of CTs will hit their saturation limit and provide a similar level of saturated current to the relays. For a fault level below the saturation limit (i.e. high impedance earth fault), the CT's will not saturate and provide some level of secondary current to the relays with a guaranteed error of 10%. How do we ensure the differential relays do not trip with this level of error? Is it just a matter of decreasing the sensitivity such that they only trip for currents >10% of 20x In? For example, 10% of 20 x 1250 = 2500A?
For transformer differential, the CT's are new and are both feeding into one electronic differential protection relay (ie. by Schneider). Supplier of the switchboard feeding the transformer has nominated class Px CT's (i.e. 1250/1A .025PX100R1.5). My understanding of this notation is that, 100 is the knee point voltage (i.e. where CT saturates), R1.5 is the CT winding resistance, however what does the 0.025 mean? Also, as the knee point is given in terms of voltage and not a multiple of ratio, how do you know what level of primary current will force the CT into saturation? If you don't know this level of current, how do you ensure both sets of CT's (i.e. upstream/downstream of the transformer) will be sized such that they do not trip on through faults?
Thanks
