Today is...
Tuesday, June 19, 2018
Welcome to, the global online
community of automation professionals.
Featured Video...
Featured Video
EtherCAT with CTC’s master lets your multivendor network play well together...
Our Advertisers
Help keep our servers running...
Patronize our advertisers!
Visit our Post Archive
Need a Simple lesson on LSTG MarkV
I need a brief description of how LSTG's MarkV valve test works

I would like the description to provide me with the similarities or differences with the logic of the MarkI/II circuits.
for example, the MarkI/II valve test could be described as

1) the valve position sums the desired valve position with the actual to derive an error signal that is convert to a current for the servo valve.

2) the gain of the valve position is such that an approximately 5% error produces a 100% servo current.

3) to limit the opening rate of a valve, a ceiling limiter is applied to the current to limit the servo for a 10%/second opening rate.

4) to test the valve, the ceiling limit is reduced to a value that provides a servo current to close the valve at 10%/second

5) once the valve is closed, the opening limit is reestablish, and due to the large error between the pretest desired position and the now lower position, the servo current saturates at the 10%/sec rate, till the valve returns to pretest position and returns to servo control.

So with respect to the way MarkI/II did valve test, how does MarkV do it.

My experience is with MarkI/II, but I never even seen the LSTG digital controls. I need this information to help me understand a possible actuator problem a customer is experiencing. This was a retrofit so it is the same actuators I am familiar with.

Thanks and keep it simple since I have a problem understanding that digital stuff :)

Ultimately, the position reference is summed with the actual position and any null bias is "added" to the output current. This is done at the TCQA card level.

Unfortunately, I don't recall exactly how the valve test is performed, but if I recall correctly the logic and sequencing is done in the CSP and then thereference is sent to the TCQA cards, where the summation with the LVDT feedback is done and any null bias is added to the servo current output. I believe all the rates and limits are Control Constants. When the test is enabled the normal reference is bypassed and the test reference is written to the TCQA cards. When the test is complete, the normal reference is "re-enabled."

It should be possible to review the CSP to see how the test is conducted. The key is to know which servo output is driving the valve being tested and to know the name of the signal assigned to that output. Once you know which servo output is driving the valve to be tests, you can look in F:\UNIT1 at IO.ASG and find the servo output and then determine the name of the signal assigned to that output. Armed with that information, you should be able to use the CSP Cross-Reference to fine the segment and rung where the signal is written to and then work backwards from there to see how the test is conducted.

Hope this helps!

Thanks for your reply CSA...

You were beginning to get into too much detail for what I need. I got a reply from another source that provided what he remembered.

the detail level I need would be like this;

1)test position reference is ramped down and back up at a Constant rate. the up and down rate will be the same. the operating position reference is restored once test reference exceeds
2) the normal operation maximum opening rate is set by another Constant .

Does that sound correct?

I am review some data for a low priority problem, with the though it is a hydraulic problem. So far the data received is just like most of the questions you reply to here!

reviewing the data, the above does seem to fit what I'm seeing. Given the MV test logic is so different that that of MI/II, it did make a big difference in my interpretation of what could be happening. I don't want to rely on the digital tech telling me it is a mech/hyd to explain how MV works

Sorry I can't publicly share the actual problem, even if I could, at the moment there is not enough data to ask some one what the problem could be

JFB, Jr.,

You're not the first person to ever accuse me of being too verbose, so no offense taken.

I would say your assessment of the possibilities is very close to being correct, if not right on.

I would posit that the Mark V logic, likely written by the same person who was responsible for the Mark III EHC control logic for the same tests, is very close to what was done for the Mark I/II EHC panels. The difference is the terminology, and analog versus digital implementation.

Anyway, good luck with your review and analysis. We would like to know what the solution to the unknown problem was--when you can tell us more!