C
curt wuollet
Well it would probably work, but it would cut your speed in half, doubling the number of serial read/writes. And you would need the "native" CS to go to that chip. A better way, if you want to include some hardware, would be a 1 of 8 decoder chip using 3 GPIO lines to drive it. A write to GPIO should be much less expensive in terms of time. Most simple would be to use the software select built into the expander chips, but we need the hardware select anyway for cards that don't use that particular chip. If 8 GPIO lines are not available on the CPU selected, then we might have to go with one of these routes. We can certainly add length to the backplane on the CPU end and have it run under the CPU. I suppose I should pick a CPU card and see how hard it will be to use 8 GPIO. 3 should be available on most any card. But, I hate to design to any one board as they are coming out at a rapid pace and who knows how long a particular board will be available. If the need for 8 selects will be a problem perhaps I could include copper for the decoder. Otherwise, the BP is very close to being ready for fab. PCB's design rules checking has a field day with the bus routing, but the issues are minor. Perhaps another version with the decoder for those who have a shortage of IO would be better?
Regards
cww
Regards
cww