Mark V - missing IO card

J

Thread Starter

Jarek

Hi colleagues,

In our powerplant is one GE (PG9171) gas turbines with "MkV".
during stand up the restart of MkV occured and core <R><S><T> were ub A6 state
Alarms which occured on the core <RST>

(5) DCC ERRORS
Missing IO Card
IO cfg failed
------
(1) TCQA --A7
(4) **** -- A1 //QD1 (TCDA)
(5) **** -- A1 //QD2 (TCDA)
(8) LCCQ --A7
(12) DCCQ --A7
(13) IOMA -- A7
(15) TCEI -- A7
------

Read some posts on control.com searching for the solution
Checked (Power Supply voltages and test points - geh5980)
<T,S,R> and everything is OK. I also checked 125VDC...Battery Grounds - is OK ...
<PD> core voltages measured are +65.35V and -65.42V ...

I uploaded one more time core configuraton and after the restart no changes on A6

I also switched TCDA for the new one - but it gave no changes at all - still A6 after the restart

After all these steps above on working <R,S,T> I started to disconnect "JP" pins on TCDA cards:

step 1:
1) QD1 - TCDA loc1 - "JP" - disconnected - connected ...
2) QD2 - TCDA loc1 - "JP" - disconnected - connected ...
3) core <R> gets A7 state !!!!

step 2:
1) QD1 - TCDA loc2 - "JP" - disconnected - connected ...
2) QD2 - TCDA loc2 - "JP" - disconnected - connected ...
3) Core <S> gets A7 state !!!!

step 3:
1) QD1 - TCDA loc3 - "JP" - disconnected - connected ...
2) QD2 - TCDA loc3 - "JP" - disconnected - connected ...
3) Core <T> gets A7 state !!!!

<R,S,T,C> -- are A7 !!!
Super ...
But turning off and turning on again the supply for <R,S,T> brings back errors again and A6 stare

Repeating steps 1,2,3 causes getting back to A7 state

What's wrong.... any suggestions ??

--
Jarek
 
Good bit of troubleshooting finding that by re-booting the TCDAs (which is what it's believed you did by unplugging the JP cable, which I think is the power from the TCPS of the respective core for each of the TCDAs; unfortunately, it's not shown very well in the Signal Flow Diagrams of Appendix D of the Mark V App. Manual, GEH-6195, and I don't have access to a Mark V these days).

The next thing I would say is: If you can get the processors to A7, then leave them at A7 and go for a start.

A hard re-boot is better than a soft re-boot, meaning that using the white button on the DCC/SDCC card is not always the best way to re-boot the processors.

It seems that there is some problem with the IONET communications between the processor and the TCDA cards. The IONET for <Q> runs from the processors (the TCQC, I believe) through the TCEAs and to the TCDAs (<QD1> first, then <QD2>). There is an IONET for each of the processors, one for <R>, one for <S>, and one for <T>. It seems that for some reason when the processors are being re-booted that the TCDAs are getting the information they need from the processors. And when you cycle the power (by unplugging and plugging the JP cables) to the TCDAs that they get the information they need from the processors. (I believe they need to get their I/O Configuration each time they are re-booted from the EEPROM on the DCC/SDCC card.)

Was there an outage that caused the Mark V to be powered down for some time? Was there some work done in the Mark V when it was powered down? Were PROMs changed? Were cards changed?

I was going to say did you check the jumper settings for the IONET termination jumpers (refer to the Mark V App. Manual and Maintenance Manual for details), but it wouldn't seem they would work at all if the IONET termination jumpers were incorrectly.

In the re-boot, are you powering-up the TCEAs AFTER you are applying power to the processors? If so, how long after you are applying power? It shouldn't make too much of a difference, but it might; just asking.

Again, if you can get it them to A7, go ahead and start the unit. It should be okay. But it is odd that when you "re-boot" the panel that everything is coming up okay except the TCDAs.
 
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