Idle time of processors in markv tmr control panel


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What is the idle time of processors in the markv tmr control panel?what is the physical significance of it?

Thanks & regards

During each execution of the CSP (Control Sequence Program) segment (which takes place in a "frame" which is 1/16th of a second; most heavy duty gas turbine CSP segments are only executed every other frame, or at an 8 Hz rate, meaning there is sometimes one frame between executions when no sequencing is executed--but that's for another thread), there is (should be) some portion of the frame during which nothing is happening because all the tasks have been completed. The portion of the frame after which all sequencing tasks have been completed is referred to as the "idle time"--the time the microprocessor is not performing any sequencing or any tasks.

During each frame, the following tasks take place:

1) each processor reads its inputs;
2) each processor then communicates what it believes the values of its inputs to be to the other processors;
3) each redundant control processor then votes the values of the other two redundant control processor's input (this only happens in a TMR panel...);
4) each processor then uses the voted values of inputs as it executes one "scan" of the CSP;
5) each processor then writes to its outputs using the values determined in the execution/scan of the CSP.

Any portion of the 1/16th of a second remaining after that is deemed the "idle time". When scheduled, the next execution of the CSP will occur, whether it's during the next frame or the following frame.

Typical idle times for redundant processors are approximately 30-60%--that's right! The inputs can be read, the inputs can be communicated to the other processors, each processor can then choose the voted value of the inputs, each processor can then execute one scan of the CSP using the input values it voted to determine, and then each processor can write to its outputs--and there can still be as much as 30-60% of that 1/16th of a second remaining!

Low idle times are indicative of problems processing data--either reading the inputs, communicating the inputs, voting the inputs, executing the CSP, or writing to the outputs. Usually there are Diagnostic Alarms which point to what the problem is--not always, depending on the PROM revisions, but usually.

Unlike the Mk IV, where values from the three redundant control processors were voted in <C>, each control processor, each of the redundant control processors in the Mk V votes the inputs using the values communicated from the other two control processors before executing the CSP. The Mk V requires--and uses--very tightly synchronized timing for all the processors (including <C>, which communicates the values of its inputs to the redundant control processors for use in the execution of the CSP)--which is also unlike the Mk IV, which was a very loosely synchronized system (that's why there can be so many voting mismatches on outputs like RAISE/LOWER speed reference indicating lights and Water/Steam Inj RAISE/LOWER relay outputs...).

There's one more thing which can bring a <C> processor to its knees: a problem with GSM communications. Specifically, requesting too much data or requesting it too often or even requesting data points which don't exist. (GSM is a communications protocol which the DCS uses to ask for data from Mk Vs via GE Mark V HMIs, usually via an Ethernet connection. GSM can also be used to send commands to Mk Vs via GE Mark V HMIs.)

Does your plant use GSM to get data from Mk Vs via GE Mark V HMIs?


it is clear from your reply that idle time means the time during which the processor does not perform any function, because all the sequencing have already been completed.

but some of your description i could not understand the followings:

1. the frame what it is? it is the time frame in which each csp segments are executed. csp segments are executed at the rate of 32hz, 16 hz or 8 hz. so time period is t=1/f. so if it is 16 hz than time is 1/16 sec, if 8hz than timeframe is 1/8 sec. is it right?

2. different csp segments are executed at different frequencies. suppose there are 6 csp segments in the <MSTR_SEQ.CFG> file in <R,S,T> SEGMENTS, out of which first 3 are executed at the rate of 16hz and 3 are at the rate of 8 hz. so when the processor executes first csp segment than it will execute that in 1/16 sec, but it executes it much earlier than this and this also for all csp segments.

so my question is that in the LCC display the idle time is displayed as around 40%. so how is 40%. that means is it the average summation of all the idle time of each csp segments. Because if i understood correctly than each csp segments have some idle time depending on their scan rate. so how the overall idle time is calculated, that is displayed in the LCC keypad.

3. the prosessor u are talking it is the main processor in the <DCC> card that is 80186 microprocessor, because it executes the csp.
in addition to that it has also 2 more processors that is 80196 and also 32015 (math coprocessor) in the DCC card, these two processors also contributes to this idle time.

so here my question is idle time only relates to the execution of CSP, in the <RAM>, or is it also related to some other things?

4. The other cards in the MarkV panel for example TCQA, TCQB, TCQC, TCEA (lets for <R> -core), also have 80196 processor chip, it also executes its insturctions in its RAM in that particular card.

So here my question is their idle times also taken into account while calculating the idle time or <R> core?

Thanks & Regards,
Frame: Every second is divided into 16 equal "frames." If a CSP segment is to be executed at an 8 Hz rate, it will be executed every other frame.

Frame Execution: If CSP segment SEQ_A.SRC is to be executed at a 16 Hz rate, it will be executed every frame. If two other CSP segments, SEQ_B.SRC and SEQ_C.SRC are to be executed at an 8 Hz rate, they would be executed every other frame. So, in the first frame, three segments would be executed: SEQ_Q.SRC, SEQ_B.SRC, and SEQ_C.SRC. In the second frame only one segment would be executed: SEQ_A.SRC. In the third frame three segments would be executed: SEQ_Q.SRC. SEQ_B.SRC, and SEQ_C.SRC. In the fourth frame, one segment would be executed: SEQ_A.SRC; and so on.

To make matter more complicated, there is an method to offset execution of segments which are executed at rates less than 16 Hz. So, using the segments and rates from the above example, if SEQ_C.SRC had an offset of 1, in the first frame two segments would be executed: SEQ_Q.SRC and SEQ_B.SRC. In the second frame, two segments would be executed: SEQ_A.SRC and SEQ_C.CRC. In the third frame, two segments would be executed: SEQ_A.SRC and SEQ_B.SRC. In the fourth frame, two segments would be executed: SEQ_A.SRC and SEQ_C.SRC; and so on.

Idle time of processors vs. microprocessors: This author has not given this much thought or consideration. There is very little written on the sibject of idle time, and what the percentages in each display mean. To determine the idle time of the 80186 microprocessor, one must press the LCC key in the upper left corner of the LCC Display keypad; -- 186 MONITOR -- will be shown in the display. If one presses ENTER, the percentage value shown in the display will be the idle time of the 80186 microprocessor. The presumption is then that the percentage value shown in the NORMAL display of the LCC Display is either the average idle time for the microprocessors and coprocessors in the processor core (<C>, or <R>, or <S>, or <T>, or <D>, if so equipeed), OR, this author seems to recall that it's the idle time of the communications microprocessor on the LCC/SLCC card. Again, there's very little written about idle times and displays, and unless there were unusual problems or specific Diagnostic Alarms idle times were never a major consideration.

This is true because we never get any material or reading article regarding idle time in any of the markv documents,neither in application manual nor in maintenace manual.

You said that every second is divided into 16 equal frames.this is ok.but if a csp segment is executed at 32 hz rate than each second is diveded into 32equal it right?

That means once in the file <mstr_seq.cfg>file if we define that a particular csp segment will be executed in 32 hz rate than the each second will be divided into 32 equal frames and depending on that other segments will be executed.
In this master configuration file the csp segments are executed in order that is first one will be executed first and second one will be in my question here is that is the csp segment which needs to be executed at 32 hz will be mentioned first?

That means is each second is diveded into 16 equal frames that is fixed or it can be also 32,depending on the scan rate of first csp segment which we will mentioned in the <mstr_seq.cfg>file.
Are their any factor taken into consideration while deciding the scan rate of a particular csp segment.that means how we can say that this csp segment should be executed at this rate and other one will be in other scan it depends on which sequencing they does or the criticality of the sequence?

Thanks & Regards
Other than the Mk V LM panels, this author is unaware of any Mk Vs which execute sequencing at any rates faster than 16 Hz. Can you provide information from an MSTR_SEQ.CFG file for a specific Mark V turbine control requisition/installation that has a CSP scan rate greater than 16 Hz?

One should not consider changing CSP scan rates or offsets from what they are specified to be in the MSTR_SEQ.CFG.

you are right, i have never seen in our heavy duty gas turbine any CSP segment executed more than 16hz rate. ok if i will get it from some other turbines i will tell you.

Is there any significant difference in Idle time Between Mark V A and B system? what i observed is Mark V A system has 12% idle time only and 23% in B System particularly C core.
Not that this author is aware of. The factors which most affect idle time are:

1) amount of sequencing being executed;

2) amount of data being requested by the operator interface (<I> or GE Mark V HMI--usually the GE Mk V HMI asks for significantly more data than an <I>);

3) type and number of CSP (Control Seqence Program) Complier warningss, if any.

Yes--the CSP Compiler will generate downloadable CSP files even when it annunciates warnings; common issues are incorrect scale types, improperly configured primitive blocks (compare with deadband or compare with hysteresis or arithmetic blocks with incorrect shifts, etc.). If the microprocessor has problems executing the CSP, it will cause idle time to decrease.

Check the ASCII text file MK5MAKE.LOG for any warnings generated by any of the compilers, including the CSP Compiler, which are executed when MK5MAKE.BAT is executed.

Other problems have also included improperly completed PROM upgrade procedures which resulted in improper card configuration files being used for I/O Configuration and CSP BBLs (Big Block Language "blocks").