I am having a project in my DSP class. A sample and hold circuit is needed. I hope anyone can at least share their knowledge about designing a sample and hold circuit.

 

The basics of an S/H circuit are as follows:
An analog signal is input ,through a buffer, to the source of a JFET, a sample rate TTL clock pulse is applied to the gate, and the output is taken over a parallel capacitor at the drain. A buffer should be used in series with the output.

Try this site for a visual.

Hope it helps!!

http://www.eecg.toronto.edu/~kphang/ece1352f/papers/jwong_SH.pdf

 

Try:

1) The Don Lancaster "Cookbook" series for electronics.

2) Go to a tech school / university library or bookstore, for the most recent "Guidebook of Electronic Circuit Schematics."

3) Try the REA (Research & Education Association) "Problem Solver Series" covering electronics.

Regards,
Phil Corso, PE
Boca Raton, FL
[[email protected]] ([email protected]) {[email protected]}

 

In many years, I've never seen a simple sample and hold except at very low speeds. The concept is simple, the practice is a great learning experience. In the end, you set theory aside and tweak heavily.

Regards

cww